By Eric A. Vittoz (auth.), Rudy J. van de Plassche, Willy M. C. Sansen, Johan H. Huijsing (eds.)
The attention of sign sampling and quantization at excessive pattern charges with low strength dissipation is a vital target in lots of functions, includ ing transportable video units equivalent to camcorders, own verbal exchange units comparable to instant LAN transceivers, within the learn channels of magnetic garage units utilizing electronic information detection, and so forth. This paper describes structure and circuit techniques for the layout of high-speed, low-power pipeline analog-to-digital converters in CMOS. the following the time period excessive velocity is taken to suggest sampling charges above 1 Mhz. within the first part the dif ferent conversion ideas appropriate during this variety of pattern charges is dis stubborn. Following that the actual difficulties linked to strength minimization in video-rate pipeline ADCs is mentioned. those contain optimi zation of capacitor sizes, layout of low-voltage transmission gates, and opti mization of switched capacitor achieve blocks and operational amplifiers for minimal strength dissipation. as an instance of the applying of those tech niques, the layout of a power-optimized lO-bit pipeline reduction converter (ADC) that achieves =1. sixty seven mW according to MS/s of sampling price from 1 MS/s to twenty MS/s is defined. 2. ideas for CMOS Video-Rate reduction Conversion Analog-to-digital conversion ideas may be classified in lots of methods. One handy technique of evaluating concepts is to envision the variety of "analog clock cycles" required to supply one potent output pattern of the sign being quantized.
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Additional resources for Analog Circuit Design: Low-Power Low-Voltage, Integrated Filters and Smart Power
Successive approximation requires about 12 clocks, and flash, half-flash, and pipelined ADCs require on the order of one clock cycle. For sampling rates in the 5Msample/sec range and above, flash, multi-step flash, and pipelined approaches are required to achieve the throughput rates needed in technologies readily available today. Flash, Pipeline 14- / t=1 Succs. Resol 10 _ utlon a6_ Clock Cycles per output sample Fig. 1 Qualitative Comparison of AID Conversion Techniques S2 From a power dissipation perspective, full flash ADCs are attractive only at low resolution levels where the number of comparators is small and their offset is non-critical, allowing the use of fully dynamic implementations.
Secondly, the base-emitter capacitor of the output transistor, QIt loads the emitter of Q2' resulting in a second pole. Using the Miller compensation around the whole stage, the second pole causes peaking, as is shown in Fig. 33. This can be suppressed by inserting an additional Miller capacitor CMO . This results in a factor two reduction of the unity-gain frequency. Fig. 32. Darlington output stage. The current gain of a bipolar transistors can also be increased by using the Widlar stage, as is shown in Fig.
The minimum supply voltage is also larger than the Darlington stage. 45 r - - - - - - - - f l vpp Cm2 r--~---r---r-4Vwt Cm1 J I Fig. 37. BiCMOS Darlington stage A much better frequency behavior is obtained with the two-stage Multipath configuration as shown in Fig. 38. 9 V. r - - - - - r - - - __ vpp ~--~-~---~-~--VNN Fig. 38. BiCMOS multipath driven output stage VII. Conclusions The maximum dynamic range of low-voltage low-power amplifiers is squeezed between the low supply-voltages and the larger thennal noise voltages caused by the lower supply currents.
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