Advanced Parallel Processing Technologies: 8th International by Liqiang He, Cha Narisu (auth.), Yong Dou, Ralf Gruber, Josef

By Liqiang He, Cha Narisu (auth.), Yong Dou, Ralf Gruber, Josef M. Joller (eds.)

This e-book constitutes the refereed court cases of the eighth foreign Workshop on complicated Parallel Processing applied sciences, APPT 2009, held in Rapperswil, Switzerland, in August 2009.

The 36 revised complete papers awarded have been rigorously reviewed and chosen from seventy six submissions. All present facets in parallel and dispensed computing are addressed starting from and software program concerns to algorithmic facets and complex purposes. The papers are equipped in topical sections on structure, graphical processing unit, grid, grid scheduling, cellular software, parallel program, parallel libraries and performance.

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1. The lightweight shared cache The proposed lightweight shared cache consists of two structures as shown in figure 1: (1) The Shared Data Cache (SDC) that maintains both local data blocks and corresponding directory vectors recently cached by L1 caches. In SDC, a cache line contains tag, coherence state, directory vector and data block. Because the goal of SDC is to reduce L1 cache miss latencies, the SDC should be able to contain the blocks recently cached by L1 caches, larger SDC will waste on-chip resource.

8. : Design and Performance of Directory Caches for Scalable Shared Memory Multiprocessors. In: Fifth International Conference on High Performance Computer Architecture, HPCA-5 (1999) 9. : Switch Cache: A Framework for Improving the Remote Memory Access Latency of CC-NUMA Multiprocessors. In: 5th Int’l. Symposium on High-Performance Computer Architecture (HPCA-5), January 1999, pp. 152–160 (1999) 10. : An architecture for highperformance scalable shared- memory multiprocessors exploiting on-chip integration.

2 Cache Coherence Protocol for Lightweight Shared Cache The proposed lightweight shared cache design requires a cache coherence protocol similar to MSI [14] with some minor modifications. These modifications are performed to ensure that the lightweight shared cache can intercept and capture the messages transmitted between L1 caches and local L2 cache bank to handle all operations related to coherence maintenance. Although implementing a full-map MSI protocol, the proposed cache scheme has no special limits to directory-based coherence protocol.

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Advanced Parallel Processing Technologies: 8th International by Liqiang He, Cha Narisu (auth.), Yong Dou, Ralf Gruber, Josef
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